View APW7120_541600.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

APW7120
5V to 12V Supply Voltage, 8-PIN, Synchronous Buck PWM Controller
Features
* * *
Operating with Single 5~12V Supply Voltage or two Supply Voltages Drive Dual Low Cost N-Channel MOSFETs - Adaptive Shoot-Through Protection Built-in Feedback Compensation - Voltage-Mode PWM Control - 0~100% Duty Ratio - Fast Transient Response
General Description
The APW7120 is a fixed 300kHz frequency, voltage mode, synchronous PWM controller. The device drives two low cost N-channel MOSFETs and is designed to work with single 5~12V or two supply voltage(s), providing excellent regulation for load transients. The APW7120 integrates controls, monitoring and protection functions into a single 8-pin package to provide a low cost and perfect power solution. A power-on-reset (POR) circuit monitors the VCC supply voltage to prevent wrong logic controls. An internal 0.8V reference provides low output voltage down to 0.8V for further applications. An built-in digital soft-start with fixed soft-start interval prevents the output voltage from overshoot as well as limiting the input current. The controller' over-current protection s monitors the output current by using the voltage drop across the low-side MOSFET' RDS(ON), eliminating the s need of a current sensing resistor. Additional under voltage and over voltage protections monitor the voltage on FB pin for short-circuit and over-voltage protections. The over-current protection cycles the soft-start function until 4 over-current events are counted. Pulling and holding the voltage on OCSET pin below 0.15V with an open drain device shuts down the controller.
*
2% 0.8V Reference - Over Line, Load Regulation and Operating Temp.
* * * * *
Programmable Over-Current Protection - Using RDS(ON) of Low-Side MOSFET Hiccup-Mode Under-Voltage Protection 118% Over-Voltage Protection Adjustable Output Voltage Small Converter Size - 300kHz Constant Switching Frequency - Small SOP-8 Package
* * *
Built-In Digital Soft-Start Shutdown Control using an External MOSFET Lead Free Available (RoHS Compliant)
Applications
* * *
Motherboard Graphics Card High Current, up to 20A, DC-DC Converters
Pinouts
BOOT 1 UGATE 2 GND 3 LGATE 4 8 PHASE 7 OCSET 6 FB 5 VCC
SOP-8
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006 1 www.anpec.com.tw
APW7120
Ordering and Marking Information
APW7120 Lead Free Code Handling Code Temp. Range Package Code APW7120 K : APW7120 XXXXX Package Code K : SOP-8 Operating Ambient Temp. Range E : -20 to 70 C Handling Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
Block Diagram
VCC
3VCC 40uA
Regulator Power On Reset
OCSET
OC Enable Soft-Start and Fault Logic 0.15V 0.4V 2.5V
3VCC 67%VREF UV
POR
BOOT UGATE
Inhibit Gate Control PWM 3VCC
OV 118%VREF Soft-Start
PHASE
FB
Gm Amplifier
COMP
VREF 0.8V
LGATE
Oscillator FOSC 300kHz
GND
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
2
www.anpec.com.tw
APW7120
Application Circuit
VBIAS
+5V/12V
C2 0.1uF
2 8
D1 1N4148 C5 1uF
L1 1uH
VIN
C3, C4 820uF x2
+5/12V
BOOT
1
R4 2.2
5 VCC
UGATE
Q1 APM2512
PHASE
C1 1uF
6
U 1 OCSET APW7120
FB LGATE GND 3
7
R5
L2 1.5uH Q2 APM2512
VOUT
C6, C7 1000uF x2
1.8V/15A
4
R1 1.5k
Shutdown
Q3 2N7002
R2 1.2k C8 0.1uF R3 200
C3, C4 : 820F/16V , ESR=25 m C6, C7 : 1000F/6.3V, ESR=30 m
Absolute Maximum Ratings
Symbol VCC VBOOT Parameter VCC Supply Voltage (VCC to GND) BOOT Voltage (BOOT to PHASE) UGATE Voltage (UGATE to PHASE) <400nS pulse width >400nS pulse width LGATE Voltage (LGATE to GND) <400nS pulse width >400nS pulse width PHASE Voltage (PHASE to GND) <400nS pulse width >400nS pulse width VI/O Input Voltage (OCSET, FB to GND) Maximum Junction Temperature TSTG TSDR VESD Storage Temperature Maximum Soldering Temperature, 10 Seconds Minimum ESD Rating (Human Body Mode) (Note 2) -10 ~ 30 -0.3 ~ 16 -0.3 ~ 7 150 -65 ~ 150 300 2 V V
o o o
Rating -0.3 ~ 16 -0.3 ~ 16 -5 ~ VBOOT+0.3 -0.3 ~ VBOOT+0.3 -5 ~ VCC+0.3 -0.3 ~ VCC+0.3
Unit V V V
V
C C C
kV
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: The device is ESD sensitive. Handling precautions are recommended.
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006 3 www.anpec.com.tw
APW7120
Thermal Characteristics
Symbol JA Parameter Junction-to-Ambient Resistance in free air (Note 3) Value 160 Unit
o
C/W
Note 3: JA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions
Symbol VCC VOUT VIN IOUT TA TJ Parameter VCC Supply Voltage Converter Output Voltage Converter Input Voltage Converter Output Current Ambient Temperature Junction Temperature
(Note 4)
Range 4.5 ~ 13.2 0.8 ~ 80%VIN 2.2 ~ 13.2 0 ~ 20 -20 ~ 70 -20 ~ 125
Unit V V V A
o o
C
C
Note 4: Please refer to the typical application circuit.
Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC. Typlcal values are at TA = 25oC.
Symbol SUPPLY CURRENT IVCC
Parameter
Test Conditions
APW7120 Min Typ Max
Unit
VCC Nominal Supply Current VCC Shutdown Supply Current
UGATE and LGATE Open
3.8 0.3 250 -
2.1 1.5 4.1 0.45 300 1.5
6 4 4.4 0.6 350 -
mA mA V V kHz VP-P
POWER-ON RESET Rising VCC Threshold Hysteresis OSCILLATOR FOSC VOSC Free Running Frequency Ramp Amplitude
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
4
www.anpec.com.tw
APW7120
Electrical Characteristics (Cont.)
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC. Typlcal values are at TA = 25oC.
Symbol
Parameter
Test Conditions
APW7120 Min Typ Max
Unit
REFERENCE VOLTAGE VREF Reference Voltage Accuracy Line Regulation ERROR AMPLIFIER DC Gain FP1 FZ FP2 First Pole Frequency Zero Frequency Second Pole Frequency Average UGATE Duty Range FB Input Current PWM CONTROLLER GATE DRIVERS UGATE Source UGATE Sink LGATE Source LGATE Sink TD Dead-Time PROTECTIONS IOCSET OCSET Current Source UVFB FB Under-Voltage Threshold FB Under-Voltage Hysteresis Over-Voltage Threshold SOFT-START AND SHUTDOWN TSS Soft-Start Interval OCSET Shutdown Threshold OCSET Shutdown Hysteresis Falling VOCSET 2 0.1 3.8 0.15 40 5 0.3 mS V mV Rising VFB VPHASE=0V, Normal Operation Rising VFB 35 0.37 64 115 40 0.4 67 45 118 45 0.43 70 121 A V % mV % VBOOT-PHASE =12V, VUGATE-PHASE =6V VBOOT-PHASE =12V, VUGATE-PHASE=1V VCC=12V, VLGATE=6V VCC=12V, VLGATE=1V Guaranteed by Design 1.0 1.0 2.0 3.5 1.9 2.6 40 7 5 100 A A nS 0 86 0.4 0.4 430 85 0.1 dB Hz kHz kHz % A Measured at FB Pin TA =-20~70C VCC=12 ~ 5V -2.0 0.8 0.05 +2.0 0.5 V % %
Over-Current Reference Voltage TA =-20~70C
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
5
www.anpec.com.tw
APW7120
Functional Pin Description
BOOT (Pin 1) This pin provides ground referenced bias voltage to the high-side MOSFET driver. A bootstrap circuit with a diode connected to 5~12V is used to create a voltage suitable to drive a logic-level N-channel MOSFET. UGATE (Pin 2) Connect this pin to the high-side N-channel MOSFET' s gate. This pin provides gate drive for the high-side MOSFET. GND (Pin 3) The GND terminal provides return path for the IC' bias s current and the low-side MOSFET driver' pull-low s current. Connect the pin to the system ground via very low impedance layout on PCBs. LGATE (Pin 4) Connect this pin to the low-side N-channel MOSFET' s gate. This pin provides gate drive for the low-side MOSFET. VCC (Pin 5) Connect this pin to a 5~12V supply voltage. This pin provides bias supply for the control circuitry and the low-side MOSFET driver. The voltage at this pin is monitored for the Power-On Reset (POR) purpose. FB (Pin 6) This pin is the inverting input of the internal Gm amplifier. Connect this pin to the output (VOUT) of the converter via an external resistor divider for closedloop operation. The output voltage set by the resistor divider is determined using the following formula :
V OUT = 0.8V ( 1 + R1 ) R2 (V)
where R1 is the resistor connected from VOUT to FB , and R2 is the resistor connected from FB to GND. The FB pin is also monitored for under and over-voltage events. OCSET (Pin 7) The OCSET is a dual-function input pin for overcurrent protection and shutdown control. Connect a resistor (ROCSET) from this pin to the Drain of the lowside MOSFET. This resistor, an internal 40A current source (I OCSET), and the MOSFET' on-resistance s (RDSON) set the converter over-current trip level (IPEAK) according to the following formula:
40 A R OCSET - 0.4V (A) R DSON Pulling and holding this pin below 0.15V with an open I PEAK =
drain device, with very low parasitic capacitor, shuts down the IC with floating output and also resets the over-current counter. Releasing OCSET pin initiates a new soft-start and the converter works again. PHASE (Pin 8) The pin provides return path for the high-side MOSFET driver' pull-low current. Connect this pin to the highs side MOSFET' source. s
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
6
www.anpec.com.tw
APW7120
Typical Operating Characteristics
Reference Voltage vs Junction Temperature
0.812
Switching Frequency vs Junction Temperature
350
Switching Frequency, FOSC (kHz)
-50 -25 0 25 50 75 100
o
0.810
340 330 320 310 300 290 280 270 260 250
Reference Voltage, V REF (V)
0.808 0.806 0.804 0.802 0.800 0.798 0.796 0.794 0.792 0.790 0.788 125 150
-50
-25
0
25
50
75
100
125
150
Junction Temperature ( C)
Junction Temperature (oC)
OCSET Current vs Junction Temperature
45
VCC POR Threshold Voltage vs Junction Temperature
4.4
VCC POR Threshold Voltage (V)
44
4.3 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4
OCSET Current , I OCSET (A)
43 42 41 40 39 38 37 36 35 -50 -25 0 25 50 75 100
o
Rising VCC
Falling VCC
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature ( C)
Junction Temperature (oC)
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
7
www.anpec.com.tw
APW7120
Typical Operating Characteristics (Cont.)
OCSET Shutdown Threshold Voltage vs Junction Temperature OCSET Shutdown Threshold Voltage (V)
0.20
Falling VOCSET
0.18
0.16
0.14
0.12
0.10 -50 -25 0 25 50 75 100 125 150
Junction Temperature (oC)
Operating Waveforms
(Refer to the typical application circuit, VBAIS=VIN=+12V supplied by an ATX Power Supply) 1. Load Transient Response : IOUT = 0A -> 15A -> 0A - IOUT slew rate = 15A/S
IOUT = 0A -> 15A IOUT = 0A -> 15A -> 0A IOUT = 15A -> 0A
VOUT=1.8V VOUT
1 1
VOUT
VUGATE
3
3
VOUT
VUGATE
1
VUGATE
3
IOUT
2 2
0A
15A
IOUT
2
IOUT
Ch1 : VOUT, 100mV/Div, DC, Offset = 1.8V Ch2 : IOUT, 10A/Div Ch3 : VUGATE, 20V/Div, DC Time : 2S/Div BW = 20 MHz Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
Ch1 : VOUT, 100mV/Div, DC, Offset = 1.8V Ch2 : IOUT, 10A/Div Ch3 : VUGATE, 20V/Div, DC Time : 50S/Div BW = 20 MHz 8
Ch1 : VOUT, 100mV/Div, DC, Offset = 1.8V Ch2 : IOUT, 10A/Div Ch3 : VUGATE, 20V/Div, DC Time : 2S/Div BW = 20 MHz www.anpec.com.tw
APW7120
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply) 2. UGATE and LGATE Switching Waveforms
Rising VUGATE Falling VUGATE
IOUT = 15A
VLGATE VLGATE
VUGATE VUGATE
1,2
1,2
Ch1 : VUGATE, 5V/Div, DC Time : 20nS/Div
Ch2 : VLGATE, 2V/Div, DC BW = 500 MHz
Ch1 : VUGATE, 5V/Div, DC Ch2 : VLGATE, 2V/Div, DC Time : 20nS/Div BW = 500 MHz
3. Powering ON / OFF
Powering ON Powering OFF
IOUT = 15A
VCC VCC
IL
IL
VCC
VOUT
1,3 1,3
VOUT
IL
VOUT
2
2
IOUT = 15A
Ch1 : VCC, 2V/Div, DC Ch3 : IL, 5A/Div, DC BW = 20 MHz
Ch2 : VOUT, 1V/Div, DC Time : 5mS/Div
Ch1 : VCC, 2V/Div, DC Ch3 : IL, 5A/Div, DC BW = 20 MHz 9
Ch2 : VOUT, 1V/Div, DC Time : 5mS/Div
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
www.anpec.com.tw
APW7120
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply) 4. Enabling and Shutting Down
Enabling by Releasing OCSET Pin Shutting Down by Pulling OCSET Low
3
VOCSET
3
VOCSET
2
2
VUGATE
VUGATE
VOUT
1 1
VOUT
IOUT=2A
Ch1 : VOUT, 1V/Div, DC BW = 20 MHz
Ch2 : VUGATE, 20V/Div, DC
Ch1 : VOUT, 1V/Div, DC Ch3 : VOCSET, 2V/Div, DC BW = 20 MHz
Ch2 : VUGATE, 20V/Div, DC Time : 2mS/Div
Ch3 : VOCSET, 2V/Div, DC Time : 2mS/Div
5. Over-Current Protection
No Connecting a shutdown MOSFET at OCSET Pin Connecting a shutdown MOSFET (2N7002) at OCSET Pin
ROCSET=15k APM2512
ROCSET=15k APM2512
1
VOUT
1
VOUT
2
IL
2
IL
Ch1 : VOUT, 1V/Div, DC Time : 5mS/Div
Ch2 : IL, 10A/Div, DC BW = 20 MHz
Ch1 : VOUT, 1V/Div, DC Time : 5mS/Div
Ch2 : IL, 10A/Div, DC BW = 20 MHz
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
10
www.anpec.com.tw
APW7120
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply) 6. OCSET Voltage RC Delay
No Connecting a shutdown MOSFET at OCSET Pin Connecting a shutdown MOSFET (2N7002) at OCSET Pin
VOCSET
VOCSET
IL
IL
1,2 CProber=8pF
OCP
1,2
CProber=8pF C2N7002=44pF (measured)
OCP
Ch1 : VOCSET, 0.5V/Div, DC Time : 2S/Div
Ch2 : IL, 10A/Div, DC BW = 20 MHz
Ch1 : VOCSET, 0.5V/Div, DC Time : 2 S/Div
Ch2 : IL, 10A/Div, DC BW = 20 MHz
6. OCSET Voltage RC Delay (Cont.)
Connecting a shutdown MOSFET (APM2322) at OCSET Pin
7. Short-Circuit Test
Shorted by a wire
IL
1 UVP
OCP
OCP
OCP
OCP
VOUT
VOCSET
1,2
CProber=8pF CAPM2322=89pF (measured)
OCP
IL
2
Ch1 : VOCSET, 0.5V/Div, DC Ch2 : IL, 10A/Div, DC Time : 2S/Div BW = 20 MHz
Ch1 : VOUT, 1V/Div, DC Time : 5mS/Div
Ch2 : IL, 10A/Div, DC BW = 20 MHz
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
11
www.anpec.com.tw
APW7120
Functional Description
Power-On-Reset (POR) The APW7120 monitors the VCC voltage (VCC) for Power-On-Reset function, preventing wrong logic operation during powering on. When the VCC voltage is ready, the APW7120 starts a start-up process and then ramps the output voltage up to the target voltage. Soft-Start The APW7120 has a built-in digital soft-start to control the output voltage rise and limit the current surge at the start-up. During soft-start, an internal ramp connected to the one of the positive inputs of the Gm amplifier rises up from 0V to 2V to replace the reference voltage (0.8V) until the ramp voltage reaches the reference voltage. The soft-start interval is about 3.2ms typical, independent of the converter' input and output s voltages. Over-Current Protection(OCP) The over-current function protects the switching conv ert er against over-current or short-circuit conditions. The controller senses the inductor current by detecting the drain-to-source voltage, product of the inductor' current and the on-resistance, of the s low-side MOSFET during it' on-state. This method s enhances the converter' efficiency and reduces cost s by eliminating a current sensing resistor. A resistor (ROCSET), connected from the OCSET to the low-side MOSFET' drain, programs the over-current s trip level. An internal 40A (typical) current source flowing through the ROCSET develops a voltage (VROCSET) across the ROCSET. When the VOCSET (VROCSET+ VDS of the low-side MOSFET) is less than the internal overcurrent reference voltage (0.4V, typical), the IC shuts off the converter and then initiates a new soft-start process. After 4 over-current events are counted, the device turns off both high-side and low-side MOSFETs and the converter' output is latched to be floating. s Please pay attention to the RC delay effect. It causes the OCP trip level to be the function of the operating duty. The parasitic capacitance (including the capacitance inside the OCSET, external PCB trace capacitance and the COSS of the shutdown MOSFET) must be minimized, especially selecting a shutdown MOSFET with very small COSS. The OCP trip level follows the duty to increase a little at low operating duty, but very much at high operating duty, like the RC delay curve. Due to load regulation or current-limit, heavy load normally reduces converter' input voltage s and increases the power loses. During heavy load, the APW7120 regulates the output voltage by expending the duty. This rises up the OCP trip level at the same time. Under-Voltage Protection (UVP) The under-voltage function monitors the FB voltage (VFB) to protect the converter against short-circuit conditions. When the VFB falls below the falling UVP threshold (67% VREF ), the APW7120 shuts off the converter. After a preceding delay, which starts at the beginning of the under-voltage shutdown, the APW 7120 initiates a new soft-start to resume regulating. The under-voltage protection shuts off and then re-starts the converter repeatedly without latching. The function is disabled during soft-start process. Over-Voltage Protection (OVP) The over-voltage protection monitors the FB voltage to prevent the output from over-voltage. When the output voltage rises to 118% of the nominal output voltage, the APW7120 turns on the low-side MOSFET until the output voltage falls below the OVP threshold, regulating the output voltage around the OVP thresholds.
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
12
www.anpec.com.tw
APW7120
Functional Description (Cont.)
Adaptive Shoot-Through Protection The gate driver incorporates adaptive shoot-through protection to high-side and low-side MOSFETs from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to rise. During turn-off of the low-side MOSFET, the LGATE voltage is monitored until it reaches a 1.5V threshold, at which time the UGATE is released to rise after a constant delay. During turn-off of the high-side MOSFET, the UGATE-to-PHASE voltage is also monitored until it reaches a 1.5V threshold, at which time the LGATE is released to rise after a constant delay. Shutdown Control Pulling the OCSET voltage below 0.15V by an open drain transistor, shown in typical application circuit, shuts down the APW7120 PWM controller. In shutdown mode, the UGATE and LGATE are pulled to PHASE and GND respectively, the output is floating.
Application Information
Input Capacitor Selection Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed each time high-side MOSFET(Q1) turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of low-side MOSFET(Q2). The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current of the bulk input capacitor is calculated as the following equation : For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating.
VIN IQ1
Q1
CIN
UGATE
IL
L
IOUT V OUT ESR COUT
LGATE
Q2
ICOUT
IRMS = IOUT D (1 - D)
(A)
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
13
www.anpec.com.tw
APW7120
Application Information (Cont.)
Input Capacitor Selection (Cont.)
T=1/FOSC
ignored. Therefore the AC peak-to-peak output voltage is shown below:
VOUT = I ESR
VUGATE
DT
(V) .......... .(5)
I IOUT
IL IOUT IQ1 I ICOUT
V OUT
VOUT
Figure 1 Buck Converter Waveforms
The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern components and loads are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. An aluminum electrolytic capacitor' ESR value is s related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Output Inductor Selection
Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The output ripple is the sum of the voltages, having phase shift, across the ESR and the ideal output capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations :
V OUT = D V IN I = V OUT (1 - D) F OSC L V ESR = I ESR
(V) .......... . (1) (A) .......... .(2) (V) .......... ..(3)
The peak-to-peak voltage of the ideal output capacitor is calculated as the following equations :
V COUT = I (V) ....... (4) 8 F OSC C OUT
For general applications using bulk capacitors, the VCOUT is much smaller than the VESR and can be
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006 14
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter' response time to the load transient. The s inductor value determines the converter' ripple s current and the ripple voltage, see equations (2) and (5). Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance
www.anpec.com.tw
APW7120
Application Information (Cont.)
Output Inductor Selection (Cont.)
values reduce the converter' response time to a load s
transient. One of the parameters limiting the converter' response s to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the APW7120 will provide either 0% or 85% (Average) duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for theapplication of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:
tRISE =
L ITRAN V IN - V OUT
,
tFALL =
L ITRAN V OUT
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the transient load current. These requirements are minimum and maximum output levels for the worst case response time. MOSFET Selection The APW 7120 requires two N-Channel power MOSFETs. These should be selected based upon R DS(ON), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006 15
dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components, conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the high-side and the low-side MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). Only the high-side MOSFET has switching losses, since the low-side MOSFETs body diode or an external Schottky rectifier across the lower MOSFET clamps the switching node before the synchronous rectifier turns on. These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the low-side MOSFET' body diode. The gates charge losses are dissipated by the APW7120 and don' heat the MOSFETs. However, large gate-charge t increases the switching interval, tSW which increases the high-side MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermalresistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
1 IOUT VIN tSW FOSC 2 PLow - Side = IOUT 2 RDSON (1- D) PHigh - Side = IOUT 2 RDSON D +
Where : tSW is the switching interval Layout Considerations In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, interconnecting impedances should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and
www.anpec.com.tw
APW7120
Application Information (Cont.)
Layout Considerations (Cont.) finally combined using ground plane construction or single point grounding. Figure 2 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout: 1. Begin the layout by placing the power components first. Orient the power circuitry to chieve a clean power flow path. If possible make all the connections on one side of the PCB with wide, copper filled areas. 2. Connect the ground of feedback divider directly to the GND pin of the IC using a dedicated ground trace. 3. The VCC decoupling capacitor should be right next to the VCC and GND pins. Capacitor CBOOT should be connected as close to the BOOT and PHASE pins as possible. 4. Minimize the length and increase the width of the trace between UGATE/LGATE and the gates of the MOSFETs to reduce the impedance driving the MOSFETs.
VIN
5. Use an dedicated trace to connect the ROCSET and the Drain pad of the low-side MOSFET, Kevin connection , for accurate current sensing. 6. Keep the switching nodes (UGATE, LGATE and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore keep traces to these nodes as short as possible. 7. Place the decoupling ceramic capacitor CHF near the Drain of the high-side MOSFET as close as possible. The bulk capacitors CIN are also placed near the Drain. 8. Place the Source of the high-side MOSFET and the Drain of the low-side MOSFET as close possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. 9. Use a wide power ground plane, with low impedance, to connects the C HF , C IN , C OUT, Schottky diode and the Source of the low-side MOSFET to provide a low impedance path between the components for large and high frequency switching currents.
C HF
VCC BOOT LGATE
5 1 4
CIN +
APW7120 U 2 1UGATE PHASE 8
Q1
Q2
C OUT + L1
VOUT
Figure 2 Recommended Layout Diagram
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006 16 www.anpec.com.tw
APW7120
Package Information
SOP-8 pin ( Reference JEDEC Registration MS-012)
E
H
e1 D
e2
A1
A
1 L
0.004max.
Dim A A1 D E H L e1 e2 1
Millimeters Min. 1.35 0.10 4.80 3.80 5.80 0.40 0.33 1.27BSC 8 Max. 1.75 0.25 5.00 4.00 6.20 1.27 0.51 Min. 0.053 0.004 0.189 0.150 0.228 0.016 0.013
0.015X45
Inches Max. 0.069 0.010 0.197 0.157 0.244 0.050 0.020 0.50BSC 8
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
17
www.anpec.com.tw
APW7120
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone T L to T P
Ramp-up
Temperature
TL Tsmax
tL
Tsmin Ramp-down ts Preheat
25
t 25 C to Peak
Time
Classificatin Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds
6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006 18 www.anpec.com.tw
APW7120
Classification Reflow Profiles (Cont.)
Table 1. SnPb Entectic Process - Package Peak Reflow Temperatures 3 Package Thickness Volume mm <350 <2.5 mm 240 +0/-5C 2.5 mm 225 +0/-5C Volume mm 350 225 +0/-5C 225 +0/-5C
3
Table 2. Pb-free Process - Package Classification Reflow Temperatures Package Thickness Volume mm3 Volume mm3 Volume mm3 <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 SEC 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA
Carrier Tape & Reel Dimensions
t P P1 D
Po E
F W
Bo
Ao
Ko D1
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
19
www.anpec.com.tw
APW7120
Carrier Tape & Reel Dimensions (Cont.)
T2
J C A B
T1
Reel Dimensions
Application A 330 1 SOP- 8 F 5.5 1 B C J 2 0.5 Po T1 12.4 0.2 P1 2.0 0.1 T2 2 0.2 Ao 6.4 0.1 W 12 0. 3 Bo 5.2 0. 1 P 8 0.1 Ko E 1.750.1 t 62 +1.5 12.75+ 0.15 D D1
1.55 +0.1 1.55+ 0.25 4.0 0.1
2.1 0.1 0.30.013
(mm)
Cover Tape Dimensions
Application SOP- 8 Carrier Width 12 Cover Tape Width 9.3 Devices Per Reel 2500
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Jan., 2006
20
www.anpec.com.tw

▲Up To Search▲

Price & Availability of APW7120

	To Download APW7120 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .